The evolution of synchronous switching systems towards higher connectivity and higher transmission speeds makes it difficult to operate from a central system clock.
In a switching system able to switch data bit frames between devices attached to the switching system through transmission media such as cables or optical fibers having different lengths, the different transmission delays on the different media cause a misalignment of the frames at the input of the switching system, since at high transmission speeds, the transmission delays can reach one or several bit periods. Also the transmission delays depend upon the transmission media and upon the temperature which still increase the misalignment of the frames.
So, the realignment of the frames at the bit level and also at the frame level is necessary if it is desired not to use identical transmission media linking the switching system and the remote devices which can be located at any distance from the system.
Alignment circuits already exist. Most of the conventional techniques required signals having a frequency higher than the bit frequency of the incoming data signal to sample the incoming signal, count the phase differences between the different incoming frames in terms of sample numbers and compensate the so-measured differences.
For example, if F is the frequency of the system clock, the incoming data signals are sampled at a frequency n.F and the counts of the numbers of samples between the incoming signal transitions and the clock transitions are memorized and used to control the shifting of the data bit frames through a shift register to compensate the phase differences.
Such a solution cannot be used when the transmission frequency is too high and reaches a value which is equal to the highest possible sampling frequency.
The article published in the IEEE Journal of Solid State Circuits Vol. 23, No. 2, Apr. 1988 entitled "A 45 Mbits/s CMOS VLSI digital phase aligner" describes a circuit which generates phase compensating information by the sampling of input signal by 0.degree., 90.degree., 180.degree. and 270.degree. out of phase clock signals and then by considering the disagreements between the so-obtained samples.
This aligner circuit makes use of complex control logic circuits and only provides for a re-alignment at the bit level and not at the frame level.